package Vshift

import chisel3._
import chisel3.util._

  object VShiftInstr {

    def WIDTH128 = 128
    def WIDTH64  = 64
    def WIDTH32  = 32

    def SHL_imm_s             =     BitPat("b010111110???????010101??????????")
    def SHL_imm_v             =     BitPat("b0?0011110???????010101??????????")
    def SHLL_size_v           =     BitPat("b0?101110??100001001110??????????")
    def SHRN_imm_v            =     BitPat("b0?0011110???????100001??????????")
    def RSHRN_imm_v           =     BitPat("b0?0011110???????100011??????????")
    def SLI_imm_s             =     BitPat("b011111110???????010101??????????")
    def SLI_imm_v             =     BitPat("b0?1011110???????010101??????????")
    def SRI_imm_s             =     BitPat("b011111110???????010001??????????")
    def SRI_imm_v             =     BitPat("b0?1011110???????010001??????????")
    def SSHL_reg_s            =     BitPat("b01011110??1?????010001??????????")
    def SSHL_reg_v            =     BitPat("b0?001110??1?????010001??????????")
    def SSHLL_imm_v           =     BitPat("b0?0011110???????101001??????????")
    def SSHR_imm_s            =     BitPat("b010111110???????000001??????????")
    def SSHR_imm_v            =     BitPat("b0?0011110???????000011??????????")
    def SQRSHL_reg_s          =     BitPat("b01011110??1?????010111??????????")
    def SQRSHL_reg_v          =     BitPat("b0?001110??1?????010111??????????")
    def SQRSHRN_imm_s         =     BitPat("b010111110???????100111??????????")
    def SQRSHRN_imm_v         =     BitPat("b0?0011110???????100111??????????")
    def SQRSHRUN_imm_s        =     BitPat("b011111110???????100011??????????")
    def SQRSHRUN_imm_v        =     BitPat("b0?1011110???????100011??????????")
    def SQSHL_reg_s           =     BitPat("b01011110??1?????010011??????????")
    def SQSHL_reg_v           =     BitPat("b0?001110??1?????010011??????????")
    def SQSHL_imm_s           =     BitPat("b010111110???????011101??????????")
    def SQSHL_imm_v           =     BitPat("b0?0011110???????011101??????????")
    def SQSHLU_imm_s          =     BitPat("b011111110???????011001??????????")
    def SQSHLU_imm_v          =     BitPat("b0?1011110???????011001??????????")
    def SQSHRN_imm_s          =     BitPat("b010111110???????100101??????????")
    def SQSHRN_imm_v          =     BitPat("b0?0011110???????100101??????????")
    def SQSHRUN_imm_s         =     BitPat("b011111110???????100001??????????")
    def SQSHRUN_imm_v         =     BitPat("b0?1011110???????100001??????????")
    def SRSHL_reg_s           =     BitPat("b01011110??1?????010101??????????")
    def SRSHL_reg_v           =     BitPat("b0?001110??1?????010101??????????")
    def SRSHR_imm_s           =     BitPat("b010111110???????001001??????????")
    def SRSHR_imm_v           =     BitPat("b0?0011110???????001001??????????")
    def SRSRA_imm_s           =     BitPat("b010111110???????001101??????????")
    def SRSRA_imm_v           =     BitPat("b0?0011110???????001101??????????")
    def SSRA_imm_s            =     BitPat("b010111110???????000101??????????")
    def SSRA_imm_v            =     BitPat("b0?0011110???????000101??????????")
    def UQRSHL_reg_s          =     BitPat("b01111110??1?????010111??????????")
    def UQRSHL_reg_v          =     BitPat("b0?101110??1?????010111??????????")
    def UQRSHRN_imm_s         =     BitPat("b011111110???????100111??????????")
    def UQRSHRN_imm_v         =     BitPat("b0?1011110???????100111??????????")
    def UQSHL_reg_s           =     BitPat("b01111110??1?????010011??????????")
    def UQSHL_reg_v           =     BitPat("b0?101110??1?????010011??????????")
    def UQSHL_imm_s           =     BitPat("b011111110???????011101??????????")
    def UQSHL_imm_v           =     BitPat("b0?1011110???????011101??????????")
    def UQSHRN_imm_s          =     BitPat("b011111110???????100101??????????")
    def UQSHRN_imm_v          =     BitPat("b0?1011110???????100101??????????")
    def URSHL_reg_s           =     BitPat("b01111110??1?????010101??????????")
    def URSHL_reg_v           =     BitPat("b0?101110??1?????010101??????????")
    def URSHR_imm_s           =     BitPat("b011111110???????001001??????????")
    def URSHR_imm_v           =     BitPat("b0?1011110???????001001??????????")
    def URSRA_imm_s           =     BitPat("b011111110???????001101??????????")
    def URSRA_imm_v           =     BitPat("b0?1011110???????001101??????????")
    def USHL_reg_s            =     BitPat("b01111110??1?????010001??????????")
    def USHL_reg_v            =     BitPat("b0?101110??1?????010001??????????")
    def USHLL_imm_v           =     BitPat("b0?1011110???????101001??????????")
    def USHR_imm_s            =     BitPat("b011111110???????000001??????????")
    def USHR_imm_v            =     BitPat("b0?1011110???????000001??????????")
    def USRA_imm_s            =     BitPat("b011111110???????000101??????????")
    def USRA_imm_v            =     BitPat("b0?1011110???????000101??????????")



    def SetBit4(opBuf: UInt) :UInt= {
      val setBit = Wire(UInt(2.W))
      val a = Wire(UInt(1.W))
      val b = Wire(UInt(1.W))
      val data_temp = Wire(UInt(2.W))

      a := opBuf(3,2).orR
      data_temp := Mux(a === 1.U, opBuf(3,2), opBuf(1,0))
      b := data_temp(1) //[3:2]
      setBit    := Cat(a,b)        //[3:2]

      setBit
    }

  }

